Update Ampere title
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| <h3>Related Experience</h3> | <h3>Related Experience</h3> | ||||||
| <ul> | <ul> | ||||||
| 	<li>Ampere Principal Architect - August 2018 to present | 	<li>Ampere Principal Senior Architect - August 2018 to present | ||||||
| 		<ul> | 		<ul> | ||||||
| 		<li>Modeled performance of next-generation CPU design, allowing accurate performance projections</li> | 		<li>Modeled performance of next-generation CPU designs, allowing accurate performance projections</li> | ||||||
| 		<li>Uncovered/prevented performance and functional defects through performance validation of RTL/verilog design and (micro)architectural study</li> | 		<li>Uncovered/prevented performance and functional defects through performance validation of RTL/verilog design and (micro)architectural study</li> | ||||||
| 		<li>Proposed and studied feasibility and efficiency of potential CPU microarchitectural features</li> | 		<li>Proposed and studied feasibility and efficiency of potential CPU microarchitectural features</li> | ||||||
| 		<li>Designed and implemented methodology to collect workloads for processor performance model using QEMU, also contributing to upstream development of its plugin interface</li> | 		<li>Designed and implemented methodology to collect workloads for processor performance model using QEMU, also contributing to upstream development of its plugin interface</li> | ||||||
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